DPD-NeuralEngine: A 22-nm 6.6-TOPS/W/mm2 Recurrent Neural Network Accelerator for Wideband Power Amplifier Digital Pre-Distortion
accepted to 2025 IEEE International Symposium on Circuits and Systems (ISCAS).
AI-Native Chip Design
We explore agentic workflows and modern, machine-readable EDA foundations that connect analog circuit topology exploration with high-performance digital RTL synthesis. Our tools and benchmarks are designed for command-line automation, continuous integration and AI coding agents.

accepted to 2025 IEEE International Symposium on Circuits and Systems (ISCAS).
in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2026
2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC), Lantau, Hong Kong, 2026, pp. 170-176, 2026