01
Open · MSc thesis
AI-based Phase-Locked Loop (PLL) Calibration
Adapt learning-based calibration to phase-locked loop non-idealities.
MATLAB / SimulinkPyTorchRF fundamentals
Project details Master's thesis opportunities
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Adapt learning-based calibration to phase-locked loop non-idealities.
Co-design an efficient neural speech model and FPGA implementation for real-time voice cloning.
Design and measure an FPGA accelerator that learns to correct ADC non-idealities.
Pair low-power ADC front-ends with task-specific neural signal enhancement.