MSc thesis project
Machine Learning Accelerator for ADC Calibration on FPGA
Design and measure an FPGA accelerator that learns to correct ADC non-idealities.
**Project Description:**This project aims to design a machine learning accelerator on an FPGA for the calibration of analog-to-digital converters (ADCs). Most FPGAs provide an internal calibration algorithm for their onboard ADC. However, such conventional algorithms target a single non-ideality, whereas data-driven techniques have the potential to target all non-idealities present. Through this master thesis project, the student will gain experience in hardware/software co-design of an accelerator and in performing hands-on measurements in our laboratory with state-of-the-art equipment. The deliverable is an open-source, FPGA-specific ADC calibration accelerator implementation.
Preferred Skills: PyTorch, SystemVerilog/VHDL, FPGA design flow (Vivado)
Contact Person: Pepijn Kremers, MSc. (p.kremers@tudelft.nl) and Dr. Chang Gao (Chang.Gao@tudelft.nl)