Open Projects for Master Students

Project Description

This project builds an ultra-low-power, event-driven hardware accelerator for real-time speech processing. We will start from the open-source Neuromorphic Auditory Sensor (NAS) feature extractor and integrate it with the EdgeDRNN accelerator to perform keyword spotting (KWS) on the Google Speech Commands Dataset. The student will first implement the EdgeDRNN classifier on the NAS FPGA platform (equipped with PDM microphones and an Artix-A200 FPGA) to process spike-based audio features in real time. Following a successful FPGA prototyping phase, the student will extend the digital design to an ultra-low-power ASIC architecture.

The student has a wide range of freedom to co-design the machine learning model and the hardware. You will be encouraged to innovate on the NAS feature extraction architecture (e.g., spike-based cascade filter banks), neural network classifier algorithms (e.g., DeltaGRU or Spiking Neural Networks), model compression methods (quantization, pruning, and temporal sparsity/delta-network thresholds), and the neuromorphic hardware accelerator data path. We will target end-to-end latency, high classification accuracy, and extreme energy efficiency (performance-per-watt) down to the microwatt range. We highly welcome students with motivation in publishing their findings in top-tier solid-state circuit conferences/journals (e.g., ISSCC, VLSI, JSSC).

Ethics & consent: All standard experiments will utilize the publicly available Google Speech Commands Dataset. Any live audio testing and custom dataset recordings collected for real-time hardware evaluation must use voices with explicit written consent and adhere to privacy-preserving edge AI principles.

Preferred Skills:

• Digital IC/FPGA design (Verilog/SystemVerilog), toolflows (Xilinx Vivado, Cadence/Synopsys ASIC design flows)

• Python & PyTorch

Deliverables:

• A novel dynamically sparse neural network classifier optimized for NAS spike-based auditory features.

• Fully functional FPGA accelerator prototype on the NAS FPGA platform demonstrating real-time end-to-end KWS inference.

• Extended ultra-low-power digital ASIC design (RTL-to-GDS).

• A high-quality manuscript prepared for submission to a top-tier solid-state circuits venue.

Reference Material:

• EdgeDRNN paper: https://arxiv.org/abs/2012.13600

• pyNAVIS & NAS toolflow paper: https://doi.org/10.1016/j.neucom.2021.01.085

• pyNAVIS repository: https://github.com/jpdominguez/pyNAVIS

• OpenNAS repository: https://github.com/RTC-research-group/OpenNAS

• ASIC Baseline: A 23µW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction (ISSCC 2022): https://ieeexplore.ieee.org/document/9731708

Contact Person: Dr. Chang Gao (Chang.Gao@tudelft.nl)

The student will be supervised by Dr. Chang Gao (TU Delft) and co-supervised by Prof. Antonio Rios-Navarro (Univ. of Sevilla, Spain) and Prof. Juan P. Dominguez-Morales (Univ. of Sevilla, Spain), and Dr. Juan Manuel Montes-Sánchez.

Project Description:

This project develops an LLM-based design assistant that translates natural-language instructions into ready-to-use passive RF building blocks (inductors, transformers, matching networks) for millimeter-wave power amplifiers. You will build an AI agent that understands designer intent, orchestrates parametric PCell generation, and drives automated DRC/LVS checking and EM/Spectre verification, from a chat prompt to a validated layout.

You will have freedom to innovate on LLM tool-use mechanisms, retrieval-augmented generation over RF design knowledge, multi-objective ranking strategies, and closed-loop agent workflows with simulation feedback. Students motivated to publish at top-tier venues (e.g., IEEE IMS, TCAD, DAC) are highly welcome.

Preferred Skills:

• Python (experience with LLM APIs/frameworks is a strong plus)

• Familiarity with RF passive components and basic IC layout concepts

Deliverables:

• A working LLM-based design assistant coordinating the full passive design flow.

• End-to-end demonstration: natural-language specs → PCell generation → EM + Spectre validation.

• A high-quality manuscript for submission to a top-tier venue.

What we offer:

The student will receive a paid internship at NXP Semiconductors, working alongside experienced RF IC designers with industry-standard EDA tools and cutting-edge mm-wave design flows.

How to apply:

Interested students, please contact Dr. Chang Gao (Chang.Gao@tudelft.nl) by 30 April 2026. Candidate screening will take place in May.

Supervision: Chang Gao (TU Delft), Masoud Pashaeifar (NXP), Mark van der Heijden (NXP)

Project Description 

Analog IC design is traditionally a labor-intensive, expert-driven process. This project investigates whether state-of-the-art coding agents — Claude Code (Anthropic) and Codex (OpenAI) — can automate the full design loop of a SAR ADC, from natural-language specifications to a verified schematic.

The student will build agent workflows that: (1) translate specs into topology and sizing, (2) generate and run simulation testbenches (Cadence Spectre / Xyce / ngspice), (3) interpret results (DNL, INL, SNDR, power), and (4) iterate autonomously toward design closure. A central research question is how well current LLM agents handle the continuous, multi-objective nature of analog design, and where they fall short of human experts. There is broad freedom to innovate on agent architectures, tool-use strategies, and feedback loops. Students aiming to publish at top-tier venues (DAC, TCAD) are especially welcome.

Preferred Skills Python (LLM APIs / agent frameworks a plus); analog IC design fundamentals; familiarity with Spectre, Xyce, or ngspice; basic knowledge of layout and open-source PDKs (e.g., SKY130).

Deliverables

• A working agentic design assistant that orchestrates the SAR ADC flow from spec to verified schematic.

• A quantitative comparison of Claude Code vs. Codex (closure rate, simulation accuracy, iteration count, wall-clock time).

• End-to-end demonstration: NL specs → topology → sizing → simulation → closure.

• A manuscript targeting a top-tier venue.

References Claude Code docs; OpenAI Codex; SKY130 PDK; Xyce; Razavi, Design of Analog CMOS Integrated Circuits.

Supervision Dr. Chang Gao (Chang.Gao@tudelft.nl) and Dr. Qinwen Fan (Q.Fan@tudelft.nl), Department of Microelectronics, TU Delft.

How to Apply Send CV and transcripts to Dr. Chang Gao.

Project Description:
This project builds an energy-efficient FPGA-based accelerator for real-time voice cloning. We will start from the open-source pipeline Real-Time-Voice-Cloning (GitHub; YouTube demo) and replace the backbone TTS model with EfficientSpeech (paper) to reduce compute and memory costs while preserving naturalness. The student will co-design the model and hardware: apply quantization, pruning, and sparsity/weight-sharing to the encoder/decoder blocks, then map the kernels (mel-spectrogram, attention/FFN, vocoder) to an FPGA data path. We will prototype on the Avnet MiniZed board (MiniZed), targeting end-to-end latency, intelligibility (WER), MOS-style quality metrics, and performance-per-watt. 

Ethics & consent: all cloning experiments must use voices with explicit written consent and include a “cloned audio” watermark.

Preferred Skills:

• FPGA design (Verilog/SystemVerilog), toolflows (Vivado/Vitis)

• Python & PyTorch

Deliverables:

• Compressed EfficientSpeech-based TTS model integrated into the Real-Time-Voice-Cloning pipeline

• FPGA accelerator on MiniZed with real-time inference (encoder/decoder + vocoder offload)

Reference Material:

• Real-Time-Voice-Cloning: https://github.com/CorentinJ/Real-Time-Voice-Cloning

• Demo video: https://www.youtube.com/watch?v=-O_hYhToKoA

• EfficientSpeech paper: https://arxiv.org/abs/2305.13905

• Avnet MiniZed board: https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/minized

Contact Person:
Dr. Chang Gao (Chang.Gao@tudelft.nl)