Open PhD Position

PhD Position: Digital AI Chip Design for High‑Speed RF Systems

Opening Date: Officially in Jan 2026 but feel free to send me your CVs!

Wireless networks are becoming increasingly power-hungry, and a significant portion of that energy is consumed by the transmitter. The ERC Synergy project DISRUPT is taking a bold step: moving RF-power generation further into the digital domain and enabling new transmitter concepts, but only if we can detect imperfections and correct them in real-time.

In this PhD, you will build the digital “brain” that makes this possible: an energy-efficient, silicon-proven AI/ML accelerator for transmitter error correction (digital predistortion/calibration). Your work will sit at the intersection of machine learning, DSP, and digital IC design, and you will validate your ideas on real chips alongside an international team; thus, it is also critical for you to be a team player, communicating smoothly with your colleagues.

Your main activities will include:

Translate ML-based error‑correction / DPD algorithms into hardware-friendly forms (model reduction, sparsity, quantization, fixed‑point design).
Design the architecture and RTL of a low‑power accelerator that meets tight throughput/latency constraints.
Take the design through synthesis, layout, tape‑out, and support PCB bring‑up and measurements.
Characterize the silicon in the lab: error‑correction performance, throughput, latency, and power.
Contribute to joint demonstrators and publications with project partners.

You will be mentored day‑to‑day by Dr. Chang Gao (TU Delft) and co‑supervised by Prof. Anding Zhu (University College Dublin) and Prof. Leo de Vreede (TU Delft).

This position directly connects to DISRUPT’s planned work on efficient ML-based DPD, accelerator architecture, silicon tape‑out, and prototype measurements. More details can be found here:

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