Open Projects for Master Students

If you are interested in any project, send me your CV and transcripts to chang.gao@tudelft.nl to schedule a chat.

Neural Networks for Enhanced Analog-to-Digital Converter (ADC)

This project investigates the integration of neural networks into the signal acquisition pipeline to enhance the performance of low-resolution, low-power analog-to-digital converters (ADCs). Traditional ADCs are designed to maximize signal fidelity across a wide range of applications, but this project takes a domain-adaptive approach by pairing simplified ADC front-ends with task-specific neural post-processing to reconstruct or enhance the acquired signals.

The student will work on a prototype system built around a commercial off-the-shelf ADC (e.g., from Texas Instruments) on a PCB, and implement neural enhancement models in PyTorch to process the raw ADC outputs. The project will include hardware-in-the-loop training and inference, with optional deployment on embedded platforms such as Raspberry Pi or FPGAs. Emphasis will be placed on evaluating power, latency, and accuracy trade-offs in an end-to-end pipeline.

Preferred Skills: PyTorch, Signal Processing Fundamentals, Embedded Systems, PCB Prototyping, Verilog (optional for hardware acceleration)

Contact Person: Dr. Chang Gao (Chang.Gao@tudelft.nl)

AI-based Phase-Locked Loop (PLL) Calibration

This project aims to develop an AI-driven calibration system for phase-locked loop (PLL) non-idealities, such as jitter, phase noise, and locking instability, by adapting the OpenDPD framework, traditionally used for power amplifier linearization. Leveraging MATLAB for system-level PLL modeling and PyTorch for training neural networks, the project will automate the identification and compensation of non-linear behaviors in mixed-signal circuits. The deliverable: An open-source simulation package enabling AI-calibrated PLLs for high-precision communication systems.

Preferred Skills: MATLAB/Simulink, PyTorch, RF system fundamentals.

Contact Person: Dr. Masoud Babaie (M.Babaie@tudelft.nl) and Dr. Chang Gao (Chang.Gao@tudelft.nl)

AI-Driven Software/Hardware Co-Design for Energy-Efficient Neural Network Accelerators

Project Description:
This project focuses on leveraging AI-driven automation to co-design neural network accelerators for real-time edge applications. The goal is to integrate software optimization techniques such as quantization and pruning with hardware-aware neural network training to develop an energy-efficient accelerator on FPGA and ASIC platforms. By automating the end-to-end design process using reinforcement learning and AI-driven reasoning, the project aims to bridge the gap between deep learning frameworks and hardware implementation. Open-source EDA tools and PDKs (such as OpenLANE and Skywater 130nm) will be explored for full-stack design validation.

Preferred Skills:

Deep Learning frameworks (PyTorch, TensorFlow)
Hardware Description Languages (Verilog/SystemVerilog)
FPGA/ASIC design flow (Vivado, OpenLANE, Cadence)
Contact Person: MSc Ang Li (ang.li@tudelft.nl) and Dr. Chang Gao (Chang.Gao@tudelft.nl)

AutoVProcessor: End-to-End Automation of Neural Network Vector Processor Design Using DeepSeek-R1

This project aims to leverage DeepSeek-R1 to automate the end-to-end design of neural network vector processors, from PyTorch code compilation to RTL optimization, synthesis, place-and-route, and PCB design, using open-source tools like Skywater 130nm PDK and OpenLANE. By integrating AI-driven reasoning into hardware design, the project tackles the inefficiencies of manual IC development, enabling rapid, fully automated generation of power- and area-optimized processors. Deliverable: An open-source toolchain for AI-driven hardware design validated on FPGA/ASIC platforms.

Preferred Skills: PyTorch, Verilog, EDA tools (OpenLANE/Cadence), reinforcement learning.

Reference Material: https://arxiv.org/pdf/2305.13243

A 12-nm Sparse AI-DPD ASIC Accelerator

This project aims to design a 12-nm ASIC accelerator tailored for AI-driven Digital Pre-Distortion (DPD) in 6G mmWave communication systems. Running at a 4GHz sample rate, the accelerator must process 256 Gbps of DPD data, achieving a processing speed of 2560× that of standard 4K 60FPS video rates. Leveraging sparse neural network compression techniques and models trained via the OpenDPD framework, this ASIC aims to meet the extreme speed and efficiency demands of next-generation 6G systems.

Preferred Skills: SystemVerilog, PyTorch

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